1. pipeline break Or "pipeline stall" The delay caused on a processor using pipelines when a transfer of control is taken. Normally when a control-transfer instruction a branch, conditional branch, call or trap is taken, any following instructions which have been loaded into the processors pipeline must be discarded or "flushed" and new instructions loaded from the branch destination. This introduces a delay before the processor can resume execution. "Delayed control-transfer" is a technique used to reduce this effect.
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