1. cache block cache line cache coherency Or "cache consistency" /kash koh-heern-see/ The synchronisation of data in multiple caches such that reading a memory location via any cache will return the most recent data written to that location via any other cache. Some parallel processors do not cache accesses to shared memory to avoid the issue of cache coherency. If caches are used with shared memory then some system is required to detect when data in one processors cache should be discarded or replaced because another processor has updated that memory location. Several such schemes have been devised.
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